PWM and the 89LPC932 CCU
The 89LPC932 includes a capture compare unit (CCU) which can be configured to produce the PWM outputs needed for motor speed control. The CCU is a complex module but its poor documentation means it is not clear how to set it up for this project. These notes describe the steps necessary to configure the CCU to produce PWM outputs.
Clocks
The CCU is driven by PCLK, the peripheral clock. We first need to determine what frequency PCLK is so we need to look at the 89LPC932 clock circuits. The LPC932 has several user selectable clock sources. The source used is programmed into flash memory. The LPC932 fitted to the mcb900 board is programmed to use the on chip RC clock which runs at approximately 7.373MHz. There are no functions in the RAMAP buggy that require a precise clock frequency so it is planned to use the on chip oscillator.
The clock source is divided by a prescaler DIVM (095H) to produce the CPU clock CCLK. The reset value of DIVM is 00H so CCLK equals the on chip oscillator clock frequency at reset. CCLK is divided by 2 to produce PCLK which is therefore running at a frequency of 3.68665MHz if DIZVM is not modified.
CCU Clock System
The core of the CCU is a 16 bit up/down counter. In PWM mode, the clock to this counter is derived as follows:
Clocks
The CCU is driven by PCLK, the peripheral clock. We first need to determine what frequency PCLK is so we need to look at the 89LPC932 clock circuits. The LPC932 has several user selectable clock sources. The source used is programmed into flash memory. The LPC932 fitted to the mcb900 board is programmed to use the on chip RC clock which runs at approximately 7.373MHz. There are no functions in the RAMAP buggy that require a precise clock frequency so it is planned to use the on chip oscillator.
The clock source is divided by a prescaler DIVM (095H) to produce the CPU clock CCLK. The reset value of DIVM is 00H so CCLK equals the on chip oscillator clock frequency at reset. CCLK is divided by 2 to produce PCLK which is therefore running at a frequency of 3.68665MHz if DIZVM is not modified.
CCU Clock System
The core of the CCU is a 16 bit up/down counter. In PWM mode, the clock to this counter is derived as follows:
- PCLK is fed to a 4 bit prescaler (PLLDV3:0 in the CCU control register 1 (TCR21 at 0F9H)). The purpose of the prescaler is to produce an output frequency in the range of 0.5MHz to 1.0MHz. Since our PCLK is ~3.6MHz, we need to divide it by 4 to create an input frequency of ~0.9MHz.
- The output of the divider feeds a PLL which produces an output frequency that is 32X its input frequency. In our case the output frequency is ~29MHz.
- The PLL output feeds a 10 bit prescaler in the form of a free running counter with programmable reload at overflow. The least significant 8 bit of this are in TPCR2L at 0CAH and the top 2 bits are in TPCR2H at 0CBH. The output of this counter feeds the CCU up/down timer.
- Set up the PWM module without starting the timer
- Calculate the right value for the PLL prescaler and write it to PLLDV
- Set PLLEN. Wait until this bit read 1
- Start the timer by writing to TMOD21 and TMOD20 bits
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